: A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proofавтор
: Mikhail Kovalev, Silvia Melitta Müller, Wolfgang J. Paul Издательство
: SpringerГод выпуска
: 10 MBКоличество страниц
: This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.